1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly, to a bipolar random access memory (bipolar RAM) using an emitter-coupled-logic (ECL) memory cell and peripheral circuits, which can operate on greatly reduced power consumption in both writing and reading operations.
2. Description of the Prior Art
Bipolar RAM's generally comprise an ECL memory cell, consisting of a flip-flop circuit constructed by a pair of multi-emitter transistors and electric elements, and a plurlaity of peripheral circuits for controlling the writing on reading operation in the memory cell.
Although bipolar RAM's can be used under high-speed operation, such high-speed operation entails a large current flow in the memory cell and the peripheral circuits. As a result, biploar RAM's consume large amounts of power. The higher the speed of the writing and reading operation, the greater the power consumption of the bipolar RAM. In this regard, it should be noted that a large unnecessary current flows to the peripheral circuits, particularly during the writing operation.